Details

Project TitleThreshold Logic with Electrostatically Formed Nanowire Transistors
Track Code2014-020
Short Description

A novel logic family that provides improved computing performance and efficiencies and could replace CMOS as Si transistor scaling approaches its inherent limits

#materials #nanowire #semiconductor #transistor

Abstract

A team of Northwestern and Tel Aviv University researchers have developed a novel logic family which provides computing performance and efficiency improvements.  This technology may be an excellent candidate to ultimately replace CMOS as silicon transistor scaling approaches its inherent limits. This particular invention exploits the four gates of EFN devices. By controlling the four gates independently, highly efficient circuits can be realized using far fewer transistors than required by CMOS.  Prior art seems to have been stumped by the challenge of cascading logic stages, preventing the creation of the complex circuits essential to computing. The inventors have created the first feasible and practical logic structure that exploits these devices, and is therefore a potential replacement for CMOS as a new paradigm for the next generation of computing. The modulation of current through electrostatically formed nanowires is controlled by the voltage on the four input gates.  This behavior can be interpreted as a complex four-input switching process, enabling the computation of multiple-input threshold logic functions using a single device. This logic family overcomes the challenge posed by the input-output voltage mismatch inherent to electrostatically formed nanowires and produces circuits with one-eighth the number of active logic devices and one-quarter the number of transistors required by CMOS.

 
TagsMATERIALS: nanowire, SEMICONDUCTOR: transistor
 
Posted DateApr 11, 2014 3:55 PM

Inventor(s)

Alan Sahakian*

Joseph Friedman

Inventors at Tel Aviv University

Andrey Godkin, Alex Henning, Yossi Rosenwaks

Applications

  • High-performance computing
  • General-purpose computing
  • Mobile computing
  • Low power, high speed computing
  • Compact computing

Advantages

  • Potential for high computing efficiency
  • Four independent transistor gates
  • Compact circuits
  • High tolerance

Publications

IP Status

A provisional patent application has been filed.

Contact Information

Arjan Quist, PhD
Invention Associate
(p) 847-467-0305

(e) arjan.quist@northwestern.edu